Phase Shifted Full Bridge 1500w

Phase Shifted Full Bridge

Let’s talk a bit about Phase Shifted Full Bridge Converter. I have recently designed a 1500w one. I used one of the new controller ICs, UCC28950. It looks pretty simple nowadays, as the controller does a lot itself: peak current control, programmable delays, burst mode, slope compensation, programmable threshold for synchronous rectifiers etc. Controller can be placed on primary or secondary side.
I am not going to repeat usual explanations about how the PSFB works. Resonant shim inductor charges and discharges mosfet parasitic capacitances, mosfet diode starts conducting enabling zero voltage switching, etc. I will try to talk about some additional staff which is rarely discussed and not always easy to comprehend, at least for me.
I will try to describe the switching sequences as best as I can in details. I have done simulation of the circuit in Pspice and I will try to show that the results confirm to my description.
Then I will talk a little about 2 subjects which are rarely mentioned in the description of the PSFB:
• Concept of leading and lagging legs
• Clamping Diodes
I have done some measurements with oscilloscope and oscillograms illustrating these topics are added to the text.
Below is simplified schematic of the Phase Shifted Full Bridge Converter power circuit:

1

PSFB Simplified Schematics

2

Simulation in Pspice and some explanations

Simulation results:
Period t0 to t1: Power Transfer Mode, Q3- Q2 on
Switch Q1 is turned off. In this interval, resonance of the leakage inductance Lr which is sum of inductance Lshim and leakage inductance of the transformer and parasitic capacitance Coss takes place. Coss is sum of parasitic capacitances Q1, Q2 and parasitic capacitance of the transformer.
Because the secondary side inductance is in the freewheeling state, primary winding is shorted thru Q2 and Q3 and current flowing through the secondary side of the transformer is not reflected to the primary side. The resonance current is as follows: ir(t) = I_Lr*cos(dt), *See the resonant frequency formula below.
At t= 0 switch Q1 is turned off, the primary current charges the capacitance of switch Q1 and discharges the capacitance of switch Q3. Q1 is part of leading leg. Energy needed to charge and discharge parasitic capacitances Q1 and Q3 is supplied only by Lshim. Often this energy id not sufficient to completely discharge capacitance Q3 and its body diode does not conduct. Q3 switches on with LVS, not ZVS.
Power Transfer Mode. Mosfets Q2 and Q3 are conducting. Lsec is being charged. Dsec1 is conducting.
Period t1 to t2: Dead Time Mode. Q2 switches off, mosfets Q4 switches on
Mosfet Q2 switches off, mosfets Q4 is switching on with ZVS. The resonant inductor SHIM and filter inductor Lsec are connected in series, Lsec inductance is much bigger than SHIM and its energy quickly charge/ discharge mosfets Q2 and Q4 and Q4 easily achieves ZVS – Lagging Leg effect.
Period t2 to t3: Freewheeling Mode. Mosfets Q3 and Q4 are on.
At t=t2, switch Q4 is turned on with ZVS OR LVS. Mosfets Q3 and Q4 are conducting and primary current freewheels thru them, effectively shorting primary winding. Transformer secondary voltage Vs becomes zero and both secondary side rectifiers are conducting, inductor Lsec is discharging to the load. No power is transferred from primary side at this time. Secondary voltage Vs remains zero until the current Ip reverses its direction and rise (in the negative direction) to reach the reflected output inductor current ILsec*Ns/Np. Primary current Ip changes with slope as the input voltage Vin discharges leakage inductor SHIM, and Dsec current slopes down to reach zero at t=t6. No power is delivered to the output in this mode. Lsec is discharging, both Dsec diodes are conducting.
Period t3 to t4: Dead Time Mode. Q3 switches off, mosfets Q1 switches on
Mosfet Q3 switches off, mosfets Q1 is switching on with ZVS. In real converter mosfets Q1 and Q3 do not achieve ZVS. They belong to Leading Leg. These mosfets switch on after freewheeling cycle, when SHIM energy is already depleted in some degree, and primary winding of transformer is zero after it was shorted during freewheeling cycle. Lsec is discharging thru both Dsec diodes, 2 halves of secondary windings have opposite voltages and secondary winding voltage is zero.
Period t4 to t5: Duty Cycle Loss Mode: Mosfets Q1 and Q4 are conducting.
Primary current Ip reverses its direction and rise. Transformer secondary voltage remains zero.
Inductor Lsec is discharging and both secondary side rectifiers Dsec are conducting current. This secondary current reflected to primary has polarity opposite to rising primary current. Secondary voltage Vs remain zero until the primary current Ip rises to reach the reflected output inductor current ILsec*Ns/Np at t= t5. Ipr rises with a slope as the input voltage Vin charges the leakage inductor SHIM, and Dsec current slopes down to reach zero at t=t5. No power is delivered to the output in this mode.
Period t5 to t6: Power Transfer Mode. Mosfets Q1 and 4 are on.
Power Transfer Mode. Mosfets Q1 and 4 are conducting. At t=t6 the primary current Ip is equal to the reflected output inductor current IL2*Ns/Np. The transformer secondary voltage Vs is equal to Vin*Ns/Np, and output inductor Lsec starts charging. Lsec is being charged. Dsec2 is conducting.
Period t6 to t7: Dead Time Mode. Mosfet Q4 switches off, mosfet Q2 switches on.
Mosfet Q4 switches off, mosfet Q2 is switching on with ZVS (Lagging Leg effect).
At t=t7, switch Q4 is turned off, the primary current Ip charges the capacitance of switch Q4 and discharges the capacitance of switch Q2. When switch Q2 capacitance is discharged to zero, its body diode conducts to achieve zero voltage switching condition, the transformer secondary voltage Vs becomes zero and both SR’s carry current.
Period t7 to t8: Freewheeling Mode. Mosfets Q1 and Q2 are on
Freewheeling Mode. Mosfets Q1 and Q2 are conducting
Transformer primary voltage is shorted thru Q1 and Q2 and secondary winding voltage is zero. Lsec is discharging, both Dsec diodes are conducting.
Period t8 to t9 Dead Time Mode. Mosfet Q1 switches off, mosfet Q3 switches on
Mosfet Q1 switches off, mosfet Q3 is switching on with ZLS (Leading Leg effect).
Period t9 to t10: Duty Cycle Loss Mode: Mosfets Q1 and Q4 are conducting.
Primary current again Ip reverses its direction and rise. Inductor Lsec is discharging and both secondary side rectifiers Dsec are conducting current. This secondary current reflected to primary has polarity opposite to rising primary current. Secondary voltage Vs remain zero until the primary current Ip rises to reach the reflected output inductor current ILsec*Ns/Np at t=t10. No power is transferred to the output.
Period t10 to t Mosfets Q1 and Q4 are on. see period t0 to t1
Mosfets Q1 and 4 are conducting. At t=t10 the primary current Ip is equal to the reflected output inductor current IL2*Ns/Np. The transformer secondary voltage Vs is equal to Vin*Ns/Np, and output inductor Lsec starts charging. Lsec is being charged. Dsec1 is conducting.

*The resonance frequency of the Coss and the inductor Lr is defined as:

3

Leading and Lagging Legs

It is more difficult to achieve ZVS with the power devices S1 and S2 of the primary side leading leg than with the power devices S3 and S4 of the primary side lagging leg because the energy required for resonance is provided only by resonant inductance.

The leading leg is where the power device turns on after energy circulation, whereas the lagging leg increases after energy transfer.

S1 and S2 power devices turn on after energy circulation- that’s why it is correct to name them Leading Leg. In contrast, S3 and S4 power devices turn on after the energy transfer forming the Lagging Leg. The lagging leg switches can easily achieve the ZVS under several load conditions through sufficient energy transfer from the secondary side. On the contrary, the leading leg depends only on the leakage inductance of the transformer, so it is difficult to achieve ZVS under a light load with relatively low energy transfer from the secondary side.
Bellow are oscillograms illustrating lagging and leading legs behavior.
The oscillograms show voltages on drains of mosfets of leading and lagging legs by different outputs currents 1, 15 and 25 amperes. Maximum output current of the PSFB converter under test is 60 amperes, therefore the oscillograms show ZVS and LVS by low output currents when it is difficult to achieve ZVS.
As you can see Lagging Leg achieves ZVS at 25 amperes and very low LVS at 15 amperes.
Leading led at 25 amperes has the same LVS as lagging leg at 15 amperes.

4

Clamping diodes

Placing clamping diodes between the transformer and Lr helps to reduce the secondary side rectifiers overshoot as well as reduce their switching/commutation-related losses.
There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes DB and DC provide a path for this current and prevent any ringing by clamping the transformer primary to the primary side power rails. Normally these diodes do not dissipate much power but they should be sized to carry the full primary current. The worst case power dissipated in these diodes is:

The diodes should be ultra-fast types and rated for the input voltage of the converter – VIN (410 VDC in this case).
Bellow are oscillograms showing voltage on the secondary side rectifying mosfets with and without clamping diodes.
Measurement line above is drain to source voltage. Secondary line is gate voltage.
First oscillograms show mosfets behavior with 6 ampere output current. As you see mosfets are not engaged because the output current is too small. Current go thru mosfets inner diodes.
Oscillograms below show the situation with 12 ampere current. Mosfets are engaged and current flowes thru mosfets.